This page contains the CBSE Computer Science with Python class 12 Unit-4 chapter 3 Application of Boolean Logic. You can find the solutions for chapter 3 of CBSE class 12 Computer Science with Python Exercise. So is the case if you are looking for CBSE class 12 Computer Science with Python related topic Application of Boolean Logic questions and answers for the Exercise.
Exercise
Question 1
1. One of De Morgan’s theorems states that
(x + y)' = x'y'. Simply stated, this means that logically there is no difference between:i)
A NOR and an AND gate with inverted inputs ✔
ii)
A NAND and an OR gate with inverted inputs
iii)
An AND and a NOR gate with inverted inputs
iv)
A NOR and a NAND gate with inverted inputs
Answer 1
i) A NOR and an AND gate with inverted inputs.
By De Morgan:
(x+y)' = x'y'. LHS is NOR operation; RHS is AND of complemented inputs.Question 2
2. An AND gate with ‘bubbles’ on its input performs the same function as a(n) gate:
i)
NOT
ii)
OR
iii)
NOR ✔
iv)
NAND
Answer 2
iii) NOR gate.
An AND gate with both input bubbles gives
A'·B' = (A+B)', which is exactly the NOR function.Question 3
3. How many gates would be required to implement the following Boolean expression before simplification of
X' + X(X+Z) + Y(X+Z)?i)
1
ii)
2
iii)
4
iv)
5 ✔
Answer 3
iv) 5 gates.
Before simplification, implementation needs: one NOT for
X', one OR for (X+Z), two AND gates for X(X+Z) and Y(X+Z), and one final OR gate to combine all terms.Question 4
4. The NAND and NOR gates are referred to as universal gates because either:
i)
Can be found in almost all digital circuits
ii)
Can be used to build all other types of gate ✔
iii)
Are used in all countries of the world
iv)
Were the first gates to be integrated
Answer 4
ii) NAND and NOR are universal because each can realize AND, OR, and NOT, and therefore any Boolean circuit.
Question 5
5. The Boolean expression
X = A' + B' + C' is logically equivalent to which single gate?i)
NAND ✔
ii)
NOR
iii)
AND
iv)
OR
Answer 5
i) NAND.
A' + B' + C' = (ABC)'. This is exactly the output of a 3-input NAND gate.Question 6
6. The symbol shown below is for a 2-input NAND gate:
i)
True
ii)
False ✔
Answer 6
ii) False. The shown symbol is a 2-input AND gate (no output bubble). A NAND gate would have a small bubble at the output.
Question 7
7. By applying De Morgan’s theorem to a NOR gate, two identical truth tables can be produced:
i)
True ✔
ii)
False
Answer 7
i) True. A NOR gate and its De Morgan equivalent (AND with both inputs complemented) produce identical truth tables.
Question 8
8. Give the truth table of following gate:
i)
ii)
iii)
iv)
v)
vi)
Answer 8
i) XOR gate,
Y=A⊕B=A'B+AB'A
B
Output
0
0
0
0
1
1
1
0
1
1
1
0
ii) NOR gate,
Y=(A+B)'A
B
Output
0
0
1
0
1
0
1
0
0
1
1
0
iii) AND with both inputs inverted,
Y=A'B'=(A+B)'A
B
Output
0
0
1
0
1
0
1
0
0
1
1
0
iv) NAND gate,
Y=(AB)'A
B
Output
0
0
1
0
1
1
1
0
1
1
1
0
v) AND with both inputs inverted,
Y=A'B'=(A+B)'A
B
Output
0
0
1
0
1
0
1
0
0
1
1
0
vi) NOR gate,
Y=(A+B)'A
B
Output
0
0
1
0
1
0
1
0
0
1
1
0
Question 9
9. Convert the following logic gate circuit into a Boolean expression, writing Boolean sub-expression next to
each gate.
each gate.
i)
ii)
iii)
Answer 9
i)
Gate-wise sub-expressions:
First gate (NAND) gives
X = (AB)';Second gate (NOR) gives
F = (X+C)'= ((AB)'+C)'.ii)
Gate-wise sub-expressions:
first gate (AND) gives
X = AB;second gate (OR) gives
Y = X + C = AB + C; inverter on D gives D';final gate (AND) gives F = Y·D' = (AB + C)D'.
iii)
Gate-wise sub-expressions:
inverter on
A gives A';first AND gives
X = A'B;final gate (NAND) with
C gives F = (X·C)' = (A'BC)'.Question 10
10. Draw the circuit diagram for the following using AND, OR and NOT gate(s):
i)
F(a,b,c) = a + bc'ii)
F(x,y,z) = xy + yz + xy'iii)
f(w,x,y,z) = yz' + wxy' + wxz' + wx'ziv)
f(x,y,z) = (x + y)(y + z)(z + x)Answer 10
i)
F(a,b,c) = a + bc'📝 Note: This expression is already in minimal Sum of Products form. No simplification is possible — there are no common factors, no absorption, and no redundant terms.
(ii)
F(x,y,z) = xy + yz + xy'This can be simplified as follows:
F(x, y, z)=
xy + yz + xy'=
x(y + y') + yz=
x.1 + yz (Applying complement law y + y' = 1)=
x + yz (Applying identity law x.1 = x)So, finally we have
F(x, y, z) = x + yz. So, we’ll draw the circuit diagram for x + yziii)
F(w, x, y, z) = yz' + wxy' + wxz' + wx'zThis can be simplified as follows:
F(x, y, z)=
yz' + wxy' + wxz' + wx'z=
yz' + wx(y' + z') + wx'z=
yz' + wx(yz)' + wx'z (Applying De Morgan’s law i.e., y' + z' = (yz)')We’ll start with the middle-term and merge it with the first and last terms in the expression.
iv) (x + y)(y + z)(z + x)
Question 11
11. Convert the following circuit diagram using NAND gate(s) only. Do not simplify the expression.
Answer 11
Given circuit represents
F = AB + C.Using NAND-only form (without simplification):
F = ((AB)' · C')', where C' = (C·C)'.NAND stages:
N1 = (AB)'N2 = (C·C)' = C'F = (N1·N2)' = ((AB)'·C')'Question 12
12. Draw truth table and write Boolean function for following circuit:
Remove fig no.
Answer 12
For First Circuit:
Top branch:
A and B are inverted to A' and B', then NOR gives (A'+B')' = AB, followed by NOT gives (AB)'.Bottom branch: direct AND gives
AB.Final gate:
Y = (AB)' · AB.Boolean Function
Y = (AB)'(AB) = 0Truth Table
A
B
AB
(AB)’
Y = AB . (AB)’
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
0
Hence, output is constant
0 for all input combinations.For Second Circuit:
Top branch gives XOR output
A' ⊕ B. This is then ANDed with direct B, and final NOT is applied.So,
Y = ((A' ⊕ B) · B)'.Using
A' ⊕ B = A'B' + AB, we get:So, finally,
Y=
((A' ⊕ B) · B)'=
((A'B' + AB)B)'=
(A'B'B + ABB)'=
(0 + AB)'=
(AB)'Boolean Function
Y = (AB)'Truth Table
A
B
AB
Y = (AB)’
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
For Third Circuit:
First gate is NAND with inputs
A' and B, so output is (A'B)'.Final gate is NOR with inputs
(A'B)' and C:Y = ((A'B)' + C)'Boolean Function
Y = ((A'B)' + C)' = A'B·C'Truth Table
A
B
C
A’B·C’
Y
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
0
Question 13
13. Draw the logic gate diagram for following expression using NOR gates only:
i)
f(a,b,c,d) = Σm(2,4,5,7,8)ii)
f(x,y,z) = Σm(0,1,3,4)iii)
f(w,x,y,z) = Σm(2,4,5,6,9)Answer 13
i)
f(a,b,c,d) = Σm(2,4,5,7,8)📝 Note: The function is changed to
f(a, b, c, d) instead f(a, b, c) as a three variable function can contain only 23= 8 min-terms, from 0 to 7 (min-term 8 will be invalid). So, we considered that it is a four variable function.K-Map (4 variables)
c’d’
c’d
cd
cd’
a’b’
0
0
0
1
(m0=0, m1=0, m3=0, m2=1)
a’b
1
1
1
0
(m4=0, m5=0, m7=0, m6=1)
ab
0
0
0
0
(m12=0, m13=0, m15=0, m14=0)
ab’
1
0
0
0
(m8=0, m9=0, m11=0, m10=1)
Groups:
•
m4=0100,m5=0101→ a’bc’d’ and a’bc’d → a’bc’ (d doesn’t matter) ✓
•
m5, m7→ 0101,0111→ a’bd ✓
•
m2→ alone: a’b’cd’
•
m8→ alone: ab’c’d’
So, the minimized function will be
f(a, b, c, d) = a’bc’ + a’bd + a’b’cd’ + ab’c’d’
(ii)
f(x, y, z) = Σm(0,1,3,4)K-Map (3 variables)
y’z’
y’z
yz
yz’
x’
1
1
1
0
(m0=1, m1=1, m3=1, m2=0)
x
1
0
0
0
(m4=1, m5=0, m7=0, m6=0)
Groups:
•
m1, m3= x’y’z, x’yz → x’z
•
m0, m4= x’y’z’, xy’z’ → y’z’
So, the minified function will be
f(x, y, z) = x’y’ + x’z + y’z’
iii)
f(w,x,y,z) = Σm(2,4,5,6,9)K-Map (4 variables)
y’z’
y’z
yz
yz’
w’x’
0
0
0
1
(m0=0, m1=0, m3=0, m2=1)
w’x
1
1
0
1
(m4=1, m5=1, m7=0, m6=1)
wx
0
0
0
0
(m12=0, m13=0, m15=0, m14=0)
wx’
0
1
0
0
(m8=0, m9=1, m11=0, m10=0)
Groups:
•
m4, m6→ 0100,0110→ w’xz’ ✓
•
m4, m5→ 0100,0101→ w’xy ✓
•
m2, m6→ 0010,0110→ w’yz’ ✓
•
m9 → alone; wx’y’z
So, the minimized function will be
f(w, x, y, z) = w’xz’ + w’xy’ + w’yz’ + wx’y’z
Question 14
14. Which gates are known as universal gate? Why?
Answer 14
NAND and NOR gates are known as universal gates.
Why are they called universal gates?
They are called universal because any Boolean expression and any logic circuit can be implemented using only NAND gates or only NOR gates.
In other words, using just one of these gate types, we can create all the basic gates such as:
•
NOT
•
AND
•
OR
and then build more complex circuits from them.
Example idea
•
A NOT gate can be made using a NAND gate (by joining both inputs together).
•
A NOT gate can also be made using a NOR gate (by joining both inputs together).
So, since NAND and NOR can be used to realize all other gates, they are called universal gates.
One-line Answer:
NAND and NOR gates are called universal gates because any logic gate or Boolean function can be implemented using only NAND gates or only NOR gates.
Question 15
15. Show how AND, OR, NOT gate functions can be implemented using only:
i)
NAND gate
ii)
NOR gate
Answer 15
i) Using NAND gate only
•
NOT gate:A' = (A.A)'i.e.
A NAND A•
AND gate:A.B = ((A.B)')'i.e.
(A NAND B) NAND (A NAND B)•
OR gate:A+B = ((A+B)')'= (A'.B')'= ((A.A)'.(B.B)')'i.e.
(A NAND A) NAND (B NAND B)ii) Using NOR gate only
•
NOT gate:A' = (A+A)'i.e.
A NOR A•
AND gate:A.B = ((A.B)')'= (A'+B')'= ((A NOR A) + (B NOR B))'i.e.
(A NOR A) NOR (B NOR B)•
OR gate:A+B = ((A+B)')'= (A NOR B)'i.e.
(A NOR B) NOR (A NOR B)Hence, NAND and NOR are universal gates because each one can realize NOT, AND, and OR functions.